200 citations · 520 across the 13 of their papers we have counts for
13 papers
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks
Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala +4
In-memory computing (IMC) on a monolithic chip for deep learning faces dramatic challenges on area, yield, and on-chip interconnection cost due to the ever-increasing model sizes.…
Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks
Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti +3
With the widespread use of Deep Neural Networks (DNNs), machine learning algorithms have evolved in two diverse directions -- one with ever-increasing connection density for better…
RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy
Adnan Siraj Rakin, Li Yang, Jingtao Li +5
Recently developed adversarial weight attack, a.k.a. bit-flip attack (BFA), has shown enormous success in compromising Deep Neural Network (DNN) performance with an extremely small…
Hybrid In-memory Computing Architecture for the Training of Deep Neural Networks
Vinay Joshi, Wangxin He, Jae-sun Seo +1
The cost involved in training deep neural networks (DNNs) on von-Neumann architectures has motivated the development of novel solutions for efficient DNN training accelerators. We…
Benchmarking TinyML Systems: Challenges and Direction
Colby R. Banbury, Vijay Janapa Reddi, Max Lam +14
Recent advancements in ultra-low-power machine learning (TinyML) hardware promises to unlock an entirely new class of smart applications. However, continued progress is limited by…
High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS
Shihui Yin, Xiaoyu Sun, Shimeng Yu +1
Deep learning hardware designs have been bottlenecked by conventional memories such as SRAM due to density, leakage and parallel computing challenges. Resistive devices can address…
Automatic Compiler Based FPGA Accelerator for CNN Training
Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin +4
Training of convolutional neural networks (CNNs)on embedded platforms to support on-device learning is earning vital importance in recent days. Designing flexible training hard-war…
FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer Learning
Paul N. Whatmough, Chuteng Zhou, Patrick Hansen +3
The computational demands of computer vision tasks based on state-of-the-art Convolutional Neural Network (CNN) image classification far exceed the energy budgets of mobile devices…
Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain
Chetan Singh Thakur, Jamal Molin, Gert Cauwenberghs +12
Neuromorphic engineering (NE) encompasses a diverse range of approaches to information processing that are inspired by neurobiological systems, and this feature distinguishes neuro…
Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression
Shihui Yin, Gaurav Srivastava, Shreyas K. Venkataramanaiah +3
Deep learning algorithms have shown tremendous success in many recognition tasks; however, these algorithms typically include a deep neural network (DNN) structure and a large numb…
Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations
Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen +4
We present a new back propagation based training algorithm for discrete-time spiking neural networks (SNN). Inspired by recent deep learning algorithms on binarized neural networks…
Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs
R. Tapiador, A. Rios-Navarro, A. Linares-Barranco +3
Deep learning has significantly advanced the state of the art in artificial intelligence, gaining wide popularity from both industry and academia. Special interest is around Convol…
Reducing the Model Order of Deep Neural Networks Using Information Theory
Ming Tu, Visar Berisha, Yu Cao +1
Deep neural networks are typically represented by a much larger number of parameters than shallow models, making them prohibitive for small footprint devices. Recent research shows…