63 citations · 134 across the 6 of their papers we have counts for
12 papers
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks
Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala +4
In-memory computing (IMC) on a monolithic chip for deep learning faces dramatic challenges on area, yield, and on-chip interconnection cost due to the ever-increasing model sizes.…
Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks
Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti +3
With the widespread use of Deep Neural Networks (DNNs), machine learning algorithms have evolved in two diverse directions -- one with ever-increasing connection density for better…
RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy
Adnan Siraj Rakin, Li Yang, Jingtao Li +5
Recently developed adversarial weight attack, a.k.a. bit-flip attack (BFA), has shown enormous success in compromising Deep Neural Network (DNN) performance with an extremely small…
Hybrid In-memory Computing Architecture for the Training of Deep Neural Networks
Vinay Joshi, Wangxin He, Jae-sun Seo +1
The cost involved in training deep neural networks (DNNs) on von-Neumann architectures has motivated the development of novel solutions for efficient DNN training accelerators. We…
Benchmarking TinyML Systems: Challenges and Direction
Colby R. Banbury, Vijay Janapa Reddi, Max Lam +14
Recent advancements in ultra-low-power machine learning (TinyML) hardware promises to unlock an entirely new class of smart applications. However, continued progress is limited by…
High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS
Shihui Yin, Xiaoyu Sun, Shimeng Yu +1
Deep learning hardware designs have been bottlenecked by conventional memories such as SRAM due to density, leakage and parallel computing challenges. Resistive devices can address…