461 citations · 751 across the 33 of their papers we have counts for
8 papers · 1 filter
The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems
Ronny Ronen, Adi Eliahu, Orian Leitersdorf +5
Nowadays, data-intensive applications are gaining popularity and, together with this trend, processing-in-memory (PIM)-based systems are being given more attention and have become…
FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors
Jawad Haj-Yahya, Mohammed Alser, Jeremie S. Kim +5
Modern client processors typically use one of three commonly-used power delivery network (PDN): 1) motherboard voltage regulators (MBVR), 2) integrated voltage regulators (IVR), an…
CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit
Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta +2
Data-intensive applications are poised to benefit directly from processing-in-memory platforms, such as memristive Memory Processing Units, which allow leveraging data locality and…
The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm
Kunal Korgaonkar, Ronny Ronen, Anupam Chattopadhyay +1
This paper describes an analytical modeling tool called Bitlet that can be used, in a parameterized fashion, to understand the affinity of workloads to processing-in-memory (PIM) a…
Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM based FPGA
Swagata Mandal, Sreetama Sarkar, Wong Ming Ming +2
Efficient low complexity error correcting code(ECC) is considered as an effective technique for mitigation of multi-bit upset (MBU) in the configuration memory(CM)of static random…
Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay +3
Basic Linear Algebra Subprograms (BLAS) play key role in high performance and scientific computing applications. Experimentally, yesteryear multicore and General Purpose Graphics P…
Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design
Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha +2
Basic Linear Algebra Subprograms (BLAS) and Linear Algebra Package (LAPACK) form basic building blocks for several High Performance Computing (HPC) applications and hence dictate p…
Designing Parity Preserving Reversible Circuits
Goutam Paul, Anupam Chattopadhyay, Chander Chandak
Making a reversible circuit fault-tolerant is much more difficult than classical circuit and there have been only a few works in the area of parity-preserving reversible logic desi…