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cs.LG2025
GROOT: Graph Edge Re-growth and Partitioning for the Verification of Large Designs in Logic Synthesis
Kiran Thorat, Hongwu Peng, Yuebo Luo +8
Traditional verification methods in chip design are highly time-consuming and computationally demanding, especially for large scale circuits. Graph neural networks (GNNs) have gain…
cs.LG2025
TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
Kiran Thorat, Amit Hasan, Caiwen Ding +1
Chip manufacturing is a complex process, and to achieve a faster time to market, an increasing number of untrusted third-party tools and designs from around the world are being uti…