3 citations · 5 across the 2 of their papers we have counts for
2 papers
cs.AR2018★ 2 cited
Towards an Area-Efficient Implementation of a High ILP EDGE Soft Processor
Jan Gray, Aaron Smith
In-order scalar RISC architectures have been the dominant paradigm in FPGA soft processor design for twenty years. Prior out-of-order superscalar implementations have not exhibited…
cs.AR2016★ 3 cited
GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator
Jan Gray
GRVI is an FPGA-efficient RISC-V RV32I soft processor. Phalanx is a parallel processor and accelerator array framework. Groups of processors and accelerators form shared memory clu…