155 citations · 560 across the 28 of their papers we have counts for
8 papers · 1 filter
Online Data Reduction with Spiking Neural Networks: A Temporal-Coincidence Encoder and Distributed SNN for the ePIC dRICH Detector
Pierpaolo Perticaroli, Roberto Ammendola, Andrea Biagioni +10
The dual-radiator Ring Imaging Cherenkov (dRICH) detector of the ePIC experiment at the Electron-Ion Collider (EIC) will read out 320,000 silicon photomultiplier (SiPM) chann…
Radiation tolerance tests on key components of the ePIC-dRICH readout card
S. Geminiani, B. R. Achari, N. Agrawal +60
The dual-radiator RICH (dRICH) detector of the ePIC experiment will employ over 300000 SiPM pixels as photosensors, organized into more than 1000 Photon Detection Units. Each PDU i…
Progress report on the online processing upgrade at the NA62 experiment
M. Turisini, R. Ammendola, A. Biagioni +10
A new FPGA-based low-level trigger processor has been installed at the NA62 experiment. It is intended to extend the features of its predecessor due to a faster interconnection tec…
The integrated low-level trigger and readout system of the CERN NA62 experiment
R. Ammendola, B. Angelucci, M. Barbanera +23
The integrated low-level trigger and data acquisition (TDAQ) system of the NA62 experiment at CERN is described. The requirements of a large and fast data reduction in a high-rate…
Recent results and prospects for NA62 experiment
Silvia Martellotti
The decay is theoretically one of the cleanest meson decays and so a good place to look for indirect effects of new physics complementary to LHC search…
GPU-based Real-time Triggering in the NA62 Experiment
R. Ammendola, A. Biagioni, P. Cretaro +17
Over the last few years the GPGPU (General-Purpose computing on Graphics Processing Units) paradigm represented a remarkable development in the world of computing. Computing for Hi…
NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features
A. Lonardo, F. Ameli, R. Ammendola +14
While the GPGPU paradigm is widely recognized as an effective approach to high performance computing, its adoption in low-latency, real-time systems is still in its early stages. A…
NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems
Roberto Ammendola, Andrea Biagioni, Riccardo Fantechi +13
We implemented the NaNet FPGA-based PCI2 Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input da…