200 citations · 513 across the 24 of their papers we have counts for
12 papers · 1 filter
CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories
Man Shi, Steven Colleman, Charlotte VanDeMieroop +4
Deep neural networks (DNN) use a wide range of network topologies to achieve high accuracy within diverse applications. This model diversity makes it impossible to identify a singl…
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge
Vikram Jain, Matheus Cavalcante, Nazareno Bruschi +6
Emerging deep neural network (DNN) applications require high-performance multi-core hardware acceleration with large data bursts. Classical network-on-chips (NoCs) use serial packe…
Benchmarking and modeling of analog and digital SRAM in-memory computing architectures
Pouya Houshmand, Jiacong Sun, Marian Verhelst
In-memory-computing is emerging as an efficient hardware paradigm for deep neural network accelerators at the edge, enabling to break the memory wall and exploit massive computatio…
SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators
Victor J. B. Jung, Arne Symons, Linyan Mei +2
To meet the growing need for computational power for DNNs, multiple specialized hardware architectures have been proposed. Each DNN layer should be mapped onto the hardware with th…
TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge
Vikram Jain, Sebastian Giraldo, Jaro De Roose +3
Extreme edge devices or Internet-of-thing nodes require both ultra-low power always-on processing as well as the ability to do on-demand sampling and processing. Moreover, support…
Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators
Arne Symons, Linyan Mei, Steven Colleman +3
As the landscape of deep neural networks evolves, heterogeneous dataflow accelerators, in the form of multi-core architectures or chiplet-based designs, promise more flexibility an…
DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling
Linyan Mei, Koen Goetschalckx, Arne Symons +1
DNN workloads can be scheduled onto DNN accelerators in many different ways: from layer-by-layer scheduling to cross-layer depth-first scheduling (a.k.a. layer fusion, or cascaded…
DPU-v2: Energy-efficient execution of irregular directed acyclic graphs
Nimish Shah, Wannes Meert, Marian Verhelst
A growing number of applications like probabilistic machine learning, sparse linear algebra, robotic navigation, etc., exhibit irregular data flow computation that can be modeled w…
DPU: DAG Processing Unit for Irregular Graphs with Precision-Scalable Posit Arithmetic in 28nm
Nimish Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao +2
Computation in several real-world applications like probabilistic machine learning, sparse linear algebra, and robotic navigation, can be modeled as irregular directed acyclic grap…
Acceleration of probabilistic reasoning through custom processor architecture
Nimish Shah, Laura I. Galindez Olascoaga, Wannes Meert +1
Probabilistic reasoning is an essential tool for robust decision-making systems because of its ability to explicitly handle real-world uncertainty, constraints and causal relations…
ProbLP: A framework for low-precision probabilistic inference
Nimish Shah, Laura I. Galindez Olascoaga, Wannes Meert +1
Bayesian reasoning is a powerful mechanism for probabilistic inference in smart edge-devices. During such inferences, a low-precision arithmetic representation can enable improved…
A 0.3-2.6 TOPS/W Precision-Scalable Processor for Real-Time Large-Scale ConvNets
Bert Moons, Marian Verhelst
A low-power precision-scalable processor for ConvNets or convolutional neural networks (CNN) is implemented in a 40nm technology. Its 256 parallel processing units achieve a peak 1…