17 citations · 53 across the 9 of their papers we have counts for
9 papers
MI6: Secure Enclaves in a Speculative Out-of-Order Processor
Thomas Bourgeat, Ilia Lebedev, Andrew Wright +3
Recent attacks have broken process isolation by exploiting microarchitectural side channels that allow indirect access to shared microarchitectural state. Enclaves strengthen the p…
Constructing a Weak Memory Model
Sizhuo Zhang, Muralidaran Vijayaraghavan, Andrew Wright +2
Weak memory models are a consequence of the desire on part of architects to preserve all the uniprocessor optimizations while building a shared memory multiprocessor. The efforts t…
HGum: Messaging Framework for Hardware Accelerators
Sizhuo Zhang, Hari Angepat, Derek Chiou
Software messaging frameworks help avoid errors and reduce engineering efforts in building distributed systems by (1) providing an interface definition language (IDL) to specify pr…
BigSparse: High-performance external graph analytics
Sang-Woo Jun, Andy Wright, Sizhuo Zhang +2
We present BigSparse, a fully external graph analytics system that picks up where semi-external systems like FlashGraph and X-Stream, which only store vertex data in memory, left o…
Weak Memory Models with Matching Axiomatic and Operational Definitions
Sizhuo Zhang, Muralidaran Vijayaraghavan, Dan Lustig +1
Memory consistency models are notorious for being difficult to define precisely, to reason about, and to verify. More than a decade of effort has gone into nailing down the definit…
Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility
Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind
The memory model for RISC-V, a newly developed open source ISA, has not been finalized yet and thus, offers an opportunity to evaluate existing memory models. We believe RISC-V sho…
An Operational Framework for Specifying Memory Models using Instantaneous Instruction Execution
Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind
There has been great progress recently in formally specifying the memory model of microprocessors like ARM and POWER. These specifications are, however, too complicated for reasoni…
Validating Simplified Processor Models in Architectural Studies
Sizhuo Zhang, Andrew Wright, Daniel Sanchez +1
Cycle-accurate software simulation of multicores with complex microarchitectures is often excruciatingly slow. People use simplified core models to gain simulation speed. However,…
Taming Weak Memory Models
Sizhuo Zhang, Arvind, Muralidaran Vijayaraghavan
Speculative techniques in microarchitectures relax various dependencies in programs, which contributes to the complexity of (weak) memory models. We show using WMM, a new weak memo…