85 citations · 188 across the 12 of their papers we have counts for
12 papers
Configurable p-Neurons Using Modular p-Bits
Saleh Bunaiyan, Mohammad Alsharif, Abdelrahman S. Abdelrahman +5
Probabilistic bits (p-bits) have recently been employed in neural networks (NNs) as stochastic neurons with sigmoidal probabilistic activation functions. Nonetheless, there remain…
MAESTRO: Multi-Agent Evaluation Suite for Testing, Reliability, and Observability
Tie Ma, Yixi Chen, Vaastav Anand +8
We present MAESTRO, an evaluation suite for the testing, reliability, and observability of LLM-based MAS. MAESTRO standardizes MAS configuration and execution through a unified int…
OffRAC: Offloading Through Remote Accelerator Calls
Ziyi Yang, Krishnan B. Iyer, Yixi Chen +4
Modern applications increasingly demand ultra-low latency for data processing, often facilitated by host-controlled accelerators like GPUs and FPGAs. However, significant delays re…
ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips
Ahmad T. Sheikh, Ali Shoker, Suhaib A. Fahmy +1
A long-standing challenge is the design of chips resilient to faults and glitches. Both fine-grained gate diversity and coarse-grained modular redundancy have been used in the past…
Resilient and Secure Programmable System-on-Chip Accelerator Offload
Inês Pinto Gouveia, Ahmad T. Sheikh, Ali Shoker +2
Computational offload to hardware accelerators is gaining traction due to increasing computational demands and efficiency challenges. Programmable hardware, like FPGAs, offers a pr…
High Throughput Multidimensional Tridiagonal Systems Solvers on FPGAs
Kamalavasan Kamalakkannan, Istvan Z. Reguly, Suhaib A. Fahmy +1
We present a design space exploration for synthesizing optimized, high-throughput implementations of multiple multi-dimensional tridiagonal system solvers on FPGAs. Re-evaluating t…
Resource-Efficient Federated Learning
Ahmed M. Abdelmoniem, Atal Narayan Sahu, Marco Canini +1
Federated Learning (FL) enables distributed training by learners using local data, thereby enhancing privacy and reducing communication. However, it presents numerous challenges re…
High-Level FPGA Accelerator Design for Structured-Mesh-Based Explicit Numerical Solvers
Kamalavasan Kamalakkannan, Gihan R. Mudalige, Istvan Z. Reguly +1
This paper presents a workflow for synthesizing near-optimal FPGA implementations for structured-mesh based stencil applications for explicit solvers. It leverages key characterist…
High Throughput 2D Spatial Image Filters on FPGAs
Abdullah Al-Dujaili, Suhaib A. Fahmy
FPGAs are well established in the signal processing domain, where their fine-grained programmable nature allows the inherent parallelism in these applications to be exploited for e…
Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays
Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
FPGA vendors have recently started focusing on OpenCL for FPGAs because of its ability to leverage the parallelism inherent to heterogeneous computing platforms. OpenCL allows prog…
Security in Automotive Networks: Lightweight Authentication and Authorization
Philipp Mundhenk, Andrew Paverd, Artur Mrowca +4
With the increasing amount of interconnections between vehicles, the attack surface of internal vehicle networks is rising steeply. Although these networks are shielded against ext…
An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units
Xiangwei Li, Abhishek Jain, Douglas Maskell +1
Coarse grained overlay architectures improve FPGA design productivity by providing fast compilation and software-like programmability. Throughput oriented spatially configurable ov…