4 papers
Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs
Ioanna Souvatzoglou, Athanasios Papadimitriou, Aitzan Sari +2
Neural Networks (NNs) are increasingly used in the last decade in several demanding applications, such as object detection and classification, autonomous driving, etc. Among differ…
On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks
Amalia Artemis Koufopoulou, Athanasios Papadimitriou, Aggelos Pikrakis +2
High-level synthesis (HLS) tools have provided significant productivity enhancements to the design flow of digital systems in recent years, resulting in highly-optimized circuits,…
Security and Reliability Evaluation of Countermeasures implemented using High-Level Synthesis
Amalia Artemis Koufopoulou, Kalliopi Xevgeni, Athanasios Papadimitriou +2
As the complexity of digital circuits increases, High-Level Synthesis (HLS) is becoming a valuable tool to increase productivity and design reuse by utilizing relevant Electronic D…
Reliability-Aware Overlay Architectures for FPGAs: Features and Design Challenges
Mihalis Psarakis
The FPGA overlay architectures have been mainly proposed to improve design productivity, circuit portability and system debugging. In this paper, we address the use of overlay arch…