100 citations · 157 across the 11 of their papers we have counts for
11 papers
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators
Qijing Huang, Minwoo Kang, Grace Dinh +5
Recent advances in Deep Neural Networks (DNNs) have led to active development of specialized DNN accelerators, many of which feature a large number of processing elements laid out…
HAO: Hardware-aware neural Architecture Optimization for Efficient Inference
Zhen Dong, Yizhao Gao, Qijing Huang +3
Automatic algorithm-hardware co-design for DNN has shown great success in improving the performance of DNNs on FPGAs. However, this process remains challenging due to the intractab…
CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAs
Zhen Dong, Dequan Wang, Qijing Huang +6
Deploying deep learning models on embedded systems has been challenging due to limited computing resources. The majority of existing work focuses on accelerating image classificati…
ProTuner: Tuning Programs with Monte Carlo Tree Search
Ameer Haj-Ali, Hasan Genc, Qijing Huang +4
We explore applying the Monte Carlo Tree Search (MCTS) algorithm in a notoriously difficult task: tuning programs for high-performance deep learning and image processing. We build…
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning
Qijing Huang, Ameer Haj-Ali, William Moses +4
The performance of the code a compiler generates depends on the order in which it applies the optimization passes. Choosing a good order--often referred to as the phase-ordering pr…
Algorithm-hardware Co-design for Deformable Convolution
Qijing Huang, Dequan Wang, Yizhao Gao +5
FPGAs provide a flexible and efficient platform to accelerate rapidly-changing algorithms for computer vision. The majority of existing work focuses on accelerating image classific…
AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning
Ameer Haj-Ali, Qijing Huang, William Moses +4
The performance of the code generated by a compiler depends on the order in which the optimization passes are applied. In high-level synthesis, the quality of the generated circuit…
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
Yifan Yang, Qijing Huang, Bichen Wu +8
Using FPGAs to accelerate ConvNets has attracted significant attention in recent years. However, FPGA accelerator design has not leveraged the latest progress of ConvNets. As a res…
Proceedings of the 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017)
Hayden Kwok-Hay So, John Wawrzynek
The 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017) was held on 22 Feb, 2017 as a co-located workshop at the 25th ACM/SIGDA International Symposium on Fie…
High Level Synthesis with a Dataflow Architectural Template
Shaoyi Cheng, John Wawrzynek
In this work, we present a new approach to high level synthesis (HLS), where high level functions are first mapped to an architectural template, before hardware synthesis is perfor…
Proceedings of the 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016)
Hayden Kwok-Hay So, John Wawrzynek
The 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016) was held on 21 Mar, 2016 as a co-located workshop at the 24th ACM/SIGDA International Symposium on Fie…