83 citations · 180 across the 15 of their papers we have counts for
16 papers
Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks
Atreya Majumdar, Marc Bocquet, Tifenn Hirtzlin +6
The implementation of current deep learning training algorithms is power-hungry, owing to data transfer between memory and logic units. Oxide-based RRAMs are outstanding candidates…
Embracing the Unreliability of Memory Devices for Neuromorphic Computing
Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein +4
The emergence of resistive non-volatile memories opens the way to highly energy-efficient computation near- or in-memory. However, this type of computation is not compatible with c…
Implementation of Ternary Weights with Resistive RAM Using a Single Sense Operation per Synapse
Axel Laborieux, Marc Bocquet, Tifenn Hirtzlin +5
The design of systems implementing low precision neural networks with emerging memories such as resistive random access memory (RRAM) is a significant lead for reducing the energy…
In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications
Bogdan Penkovsky, Marc Bocquet, Tifenn Hirtzlin +5
The advent of deep learning has considerably accelerated machine learning development. The deployment of deep neural networks at the edge is however limited by their high memory an…
Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse
Axel Laborieux, Marc Bocquet, Tifenn Hirtzlin +6
The design of systems implementing low precision neural networks with emerging memories such as resistive random access memory (RRAM) is a major lead for reducing the energy consum…
Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction
Tifenn Hirtzlin, Bogdan Penkovsky, Jacques-Olivier Klein +5
One of the most exciting applications of Spin Torque Magnetoresistive Random Access Memory (ST-MRAM) is the in-memory implementation of deep neural networks, which could allow impr…
Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays
Tifenn Hirtzlin, Marc Bocquet, Bogdan Penkovsky +5
The brain performs intelligent tasks with extremely low energy consumption. This work takes inspiration from two strategies used by the brain to achieve this energy efficiency: the…
Stochastic Computing for Hardware Implementation of Binarized Neural Networks
Tifenn Hirtzlin, Bogdan Penkovsky, Marc Bocquet +3
Binarized Neural Networks, a recently discovered class of neural networks with minimal memory requirements and no reliance on multiplication, are a fantastic opportunity for the re…
Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks
Tifenn Hirtzlin, Marc Bocquet, Jacques-Olivier Klein +4
Resistive random access memories (RRAM) are novel nonvolatile memory technologies, which can be embedded at the core of CMOS, and which could be ideal for the in-memory implementat…
In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks
Marc Bocquet, Tifenn Hirztlin, Jacques-Olivier Klein +4
RRAM-based in-Memory Computing is an exciting road for implementing highly energy efficient neural networks. This vision is however challenged by RRAM variability, as the efficient…
Spatio-temporal Learning with Arrays of Analog Nanosynapses
Christopher H. Bennett, Damien Querlioz, Jacques-Olivier Klein
Emerging nanodevices such as resistive memories are being considered for hardware realizations of a variety of artificial neural networks (ANNs), including highly promising online…
A gate-variable spin current demultiplexer based on graphene
Li Su, Xiaoyang Lin, Youguang Zhang +5
Spintronics, which utilizes spin as information carrier, is a promising solution for nonvolatile memory and low-power computing in the post-Moore era. An important challenge is to…
Exploiting the Short-term to Long-term Plasticity Transition in Memristive Nanodevice Learning Architectures
Christopher H. Bennett, Selina La Barbera, Adrien F. Vincent +2
Memristive nanodevices offer new frontiers for computing systems that unite arithmetic and memory operations on-chip. Here, we explore the integration of electrochemical metallizat…
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System
Yue Zhang, Chao Zhang, Jiang Nan +6
Current-induced domain wall motion (CIDWM) is regarded as a promising way towards achieving emerging high-density, high-speed and low-power non-volatile devices. Racetrack memory i…
Current-limiting challenges for all-spin logic devices
Li Su, Youguang Zhang, Jacques-Olivier Klein +4
All-spin logic device (ASLD) has attracted increasing interests as one of the most promising post-CMOS device candidates, thanks to its low power, non-volatility and logic-in-memor…
Cross-point architecture for spin transfer torque magnetic random access memory
Weisheng Zhao, Sumanta Chaudhuri, Celso Accoto +3
Spin transfer torque magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates to build up a true universal memory thanks to its fast write/rea…