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physics.ins-det2024★ 5 cited
Time performance of Analog Pixel Test Structures with in-chip operational amplifier implemented in 65 nm CMOS imaging process
Gianluca Aglieri Rinella, Luca Aglietta, Matias Antonelli +43
In the context of the CERN EP R&D on monolithic sensors and the ALICE ITS3 upgrade, the Tower Partners Semiconductor Co (TPSCo) 65 nm process has been qualified for use in high ene…
physics.ins-det2024
Characterisation of analogue Monolithic Active Pixel Sensor test structures implemented in a 65 nm CMOS imaging process
Gianluca Aglieri Rinella, Giacomo Alocco, Matias Antonelli +91
Analogue test structures were fabricated using the Tower Partners Semiconductor Co. CMOS 65 nm ISC process. The purpose was to characterise and qualify this process and to optimise…