5 papers
Investigation of the Physical Mechanism behind Retention Loss in FeFETs with MIFIFIS Gate Structure
Tao Hu, Zeqi Chen, Runhao Han +19
A Metal-Gate Blocking Layer (GBL)- Ferroelectric-Tunnel Dielectric Layer (TDL)-Ferroelectric -Channel Insulator (Ch.IL)-Si (MIFIFIS) structure is proposed to achieve a larger MW fo…
Unveiling Retention Loss Mechanism in FeFETs with Gate-side Interlayer by Decoupling Trapped Charges and Ferroelectric Polarization
Runhao Han, Tao Hu, Jia Yang +10
We propose a direct experimental extraction technique for trapped charges and quantitative energy band diagrams in the FeFETs with metal-insulator-ferroelectric-insulator-semicondu…
Effect of Top AlO Interlayer Thickness on Memory Window and Reliability of FeFETs With TiN/AlO/HfZrO/SiO/Si (MIFIS) Gate Structure
Tao Hu, Xinpei Jia, Runhao Han +17
We investigate the effect of top Al2O3 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistors (Si-FeFETs) with TiN/AlO/Hf$_{0.5…
Impact of the Top SiO2 Interlayer Thickness on Memory Window of Si Channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) Gate Structure
Tao Hu, Xianzhou Shao, Mingkai Bai +13
We study the impact of top SiO2 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistor (FeFET) with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS…
Impact of Top SiO2 interlayer Thickness on Memory Window of Si Channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) Gate Structure
Tao Hu, Xianzhou Shao, Mingkai Bai +13
We study the impact of top SiO2 interlayer thickness on memory window of Si channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. The memory window increases wit…