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cs.LO2025
FastLEC: Parallel Datapath Equivalence Checking with Hybrid Engines
Xindi Zhang, Furong Ye, Zhihan Chen +1
Combinational equivalence checking (CEC) remains a challenge EDA task in the formal verification of datapath circuits due to their complex arithmetic structures and the limited cap…
cs.LO2024
Revisiting Restarts of CDCL: Should the Search Information be Preserved?
Xindi Zhang, Zhihan Chen, Shaowei Cai
SAT solvers are indispensable in formal verification for hardware and software with many important applications. CDCL is the most widely used framework for modern SAT solvers, and…