14 citations · 51 across the 20 of their papers we have counts for
22 papers
GPU implementation of a resource-constrained virtual machine
Simone Li, Vladislav Brusokas, Andrei Ghita +2
One of the main reasons compute hardware becomes obsolete is software bloat: resource requirements increase for every iteration of a software product. Resource constrained VMs are…
Energy-Aware Workflow Execution: An Overview of Techniques for Saving Energy and Emissions in Scientific Compute Clusters
Lauritz Thamsen, Yehia Elkhatib, Paul Harvey +3
Scientific research in many fields routinely requires the analysis of large datasets, and scientists often employ workflow systems to leverage clusters of computers for their data…
Dynamic Loop Fusion in High-Level Synthesis
Robert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede
Dynamic High-Level Synthesis (HLS) uses additional hardware to perform memory disambiguation at runtime, increasing loop throughput in irregular codes compared to static HLS. Howev…
Compiler Support for Speculation in Decoupled Access/Execute Architectures
Robert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede
Irregular codes are bottlenecked by memory and communication latency. Decoupled access/execute (DAE) is a common technique to tackle this problem. It relies on the compiler to sepa…
Optimising Iteration Scheduling for Full-State Vector Simulation of Quantum Circuits on FPGAs
Youssef Moawad, Andrew Brown, René Steijl +1
As the field of quantum computing grows, novel algorithms which take advantage of quantum phenomena need to be developed. As we are currently in the NISQ (noisy intermediate scale…
A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis
Robert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede
Dynamically scheduled high-level synthesis (HLS) enables the use of load-store queues (LSQs) which can disambiguate data hazards at circuit runtime, increasing throughput in codes…
Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis
Robert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede
Dynamically scheduled high-level synthesis (HLS) achieves higher throughput than static HLS for codes with unpredictable memory accesses and control flow. However, excessive datafl…
Frugal Computing -- On the need for low-carbon and sustainable computing and the path towards zero-carbon computing
Wim Vanderbauwhede
The current emissions from computing are almost 4% of the world total. This is already more than emissions from the airline industry and are projected to rise steeply over the next…
Transformations for accelerator-based quantum circuit simulation in Haskell
Youssef Moawad, Wim Vanderbauwhede, René Steijl
For efficient hardware-accelerated simulations of quantum circuits, we can define hardware-specific quantum-circuit transformations. We use a functional programming approach to cre…
Value-Dependent Session Design in a Dependently Typed Language
Jan de Muijnck-Hughes, Edwin Brady, Wim Vanderbauwhede
Session Types offer a typing discipline that allows protocol specifications to be used during type-checking, ensuring that implementations adhere to a given specification. When loo…
Towards Automatic Transformation of Legacy Scientific Code into OpenCL for Optimal Performance on FPGAs
Wim Vanderbauwhede, Syed Waqar Nabi
There is a large body of legacy scientific code written in languages like Fortran that is not optimised to get the best performance out of heterogeneous acceleration devices like G…
2D Image Convolution using Three Parallel Programming Models on the Xeon Phi
Ashkan Tousimojarad, Wim Vanderbauwhede, W Paul Cockshott
Image convolution is widely used for sharpening, blurring and edge detection. In this paper, we review two common algorithms for convolving a 2D image by a separable kernel (filter…
Domain-Specific Acceleration and Auto-Parallelization of Legacy Scientific Code in FORTRAN 77 using Source-to-Source Compilation
Wim Vanderbauwhede, Gavin Davidson
Massively parallel accelerators such as GPGPUs, manycores and FPGAs represent a powerful and affordable tool for scientists who look to speed up simulations of complex systems. How…
Inferring Program Transformations from Type Transformations for Partitioning of Ordered Sets
Wim Vanderbauwhede
In this paper I introduce a mechanism to derive program transforma- tions from order-preserving transformations of vector types. The purpose of this work is to allow automatic gene…
A Reconfigurable Vector Instruction Processor for Accelerating a Convection Parametrization Model on FPGAs
Syed Waqar Nabi, Saji N. Hameed, Wim Vanderbauwhede
High Performance Computing (HPC) platforms allow scientists to model computationally intensive algorithms. HPC clusters increasingly use General-Purpose Graphics Processing Units (…
An Intermediate Language and Estimator for Automated Design Space Exploration on FPGAs
Syed Waqar Nabi, Wim Vanderbauwhede
We present the TyTra-IR, a new intermediate language intended as a compilation target for high-level language compilers and a front-end for HDL code generators. We develop the requ…
Model Coupling between the Weather Research and Forecasting Model and the DPRI Large Eddy Simulator for Urban Flows on GPU-accelerated Multicore Systems
Wim Vanderbauwhede
In this report we present a novel approach to model coupling for shared-memory multicore systems hosting OpenCL-compliant accelerators, which we call The Glasgow Model Coupling Fra…
A Parallel Task-based Approach to Linear Algebra
Ashkan Tousimojarad, Wim Vanderbauwhede
Processors with large numbers of cores are becoming commonplace. In order to take advantage of the available resources in these systems, the programming paradigm has to move toward…
An Efficient Thread Mapping Strategy for Multiprogramming on Manycore Processors
Ashkan Tousimojarad, Wim Vanderbauwhede
The emergence of multicore and manycore processors is set to change the parallel computing world. Applications are shifting towards increased parallelism in order to utilise these…
Cache-aware Parallel Programming for Manycore Processors
Ashkan Tousimojarad, Wim Vanderbauwhede
With rapidly evolving technology, multicore and manycore processors have emerged as promising architectures to benefit from increasing transistor numbers. The transition towards th…
The Glasgow Parallel Reduction Machine: Programming Shared-memory Many-core Systems using Parallel Task Composition
Ashkan Tousimojarad, Wim Vanderbauwhede
We present the Glasgow Parallel Reduction Machine (GPRM), a novel, flexible framework for parallel task-composition based many-core programming. We allow the programmer to structur…
Proceedings 5th Workshop on Programming Language Approaches to Concurrency and Communication-cEntric Software
Nobuko Yoshida, Wim Vanderbauwhede
PLACES 2013 (full title: Programming Language Approaches to Concurrency- and Communication-cEntric Software) was the sixth edition of the PLACES workshop series. After the first PL…