8 citations · 9 across the 3 of their papers we have counts for
3 papers
cs.OH2015★ 1 cited
Cracking Intel Sandy Bridge's Cache Hash Function
Zhipeng Wei, Zehan Cui, Mingyu Chen
On Intel Sandy Bridge processor, last level cache (LLC) is divided into cache slices and all physical addresses are distributed across the cache slices using an hash function. With…
cs.AR2015
Twin-Load: Building a Scalable Memory System over the Non-Scalable Interface
Zehan Cui, Tianyue Lu, Haiyang Pan +2
Commodity memory interfaces have difficulty in scaling memory capacity to meet the needs of modern multicore and big data systems. DRAM device density and maximum device count are…
cs.AR2013★ 8 cited
MIMS: Towards a Message Interface based Memory System
Licheng Chen, Tianyue Lu, Yanan Wang +7
Memory system is often the main bottleneck in chipmultiprocessor (CMP) systems in terms of latency, bandwidth and efficiency, and recently additionally facing capacity and power pr…