2 papers
cs.LO2025
FORWORD: Accelerating Formal Datapath Verification via Word-Level Sweeping
Ziyi Yang, Guangyu Hu, Xiaofeng Zhou +4
Modern circuit design process increasingly adopts high-level hardware construction languages and parameterized design methodologies to shorten development cycles and maintain high…
cs.LO2025
Functional Reduction to Speed Up Bounded Model Checking
Changyuan Yu, Wenbin Che, Hongce Zhang
Bounded model checking (BMC) is a widely used technique for formal property verification (FPV), where the transition relation is repeatedly unrolled to increasing depths and encode…