173 citations · 782 across the 61 of their papers we have counts for
14 papers · 1 filter
DCC: Data-Centric Compilation of Machine Learning Kernels for Processing-In-Memory Architectures
Peiming Yang, Sankeerth Durvasula, Ivan Fernandez +4
High-performance Host processors can integrate Processing-In-Memory (PIM) devices, which can accelerate memory-intensive kernels of Machine Learning (ML) models, including Large La…
PyGim: An Efficient Graph Neural Network Library for Real Processing-In-Memory Architectures
Christina Giannoula, Peiming Yang, Ivan Fernandez +7
Graph Neural Networks (GNNs) are emerging ML models to analyze graph-structure data. Graph Neural Network (GNN) execution involves both compute-intensive and memory-intensive kerne…
FPRaker: A Processing Element For Accelerating Neural Network Training
Omar Mohamed Awad, Mostafa Mahmoud, Isak Edo +5
We present FPRaker, a processing element for composing training accelerators. FPRaker processes several floating-point multiply-accumulation operations concurrently and accumulates…
TensorDash: Exploiting Sparsity to Accelerate Deep Neural Network Training and Inference
Mostafa Mahmoud, Isak Edo, Ali Hadi Zadeh +4
TensorDash is a hardware level technique for enabling data-parallel MAC units to take advantage of sparsity in their input operand streams. When used to compose a hardware accelera…
Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency
Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar +4
This paper summarizes the idea of ChargeCache, which was published in HPCA 2016 [51], and examines the work's significance and future potential. DRAM latency continues to be a crit…
SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure
Hasan Hassan, Nandita Vijaykumar, Samira Khan +6
This paper summarizes the SoftMC DRAM characterization infrastructure, which was published in HPCA 2017, and examines the work's significance and future potential. SoftMC (Soft Mem…
Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips
Kevin K. Chang, Abhijith Kashyap, Hasan Hassan +7
This article summarizes key results of our work on experimental characterization and analysis of latency variation and latency-reliability trade-offs in modern DRAM chips, which wa…
RowClone: Accelerating Data Movement and Initialization Using DRAM
Vivek Seshadri, Yoongu Kim, Chris Fallin +8
In existing systems, to perform any bulk data movement operation (copy or initialization), the data has to first be read into the on-chip processor, all the way into the L1 cache,…
Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko +4
This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was published in HPCA 2015, and examines the work's significance and future potential. AL-DRAM is a mechani…
Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips
Donghyuk Lee, Samira Khan, Lavanya Subramanian +5
Variation has been shown to exist across the cells within a modern DRAM chip. We empirically demonstrate a new form of variation that exists within a real DRAM chip, induced by the…
Practical Data Compression for Modern Memory Hierarchies
Gennady Pekhimenko
In this thesis, we describe a new, practical approach to integrating hardware-based data compression within the memory hierarchy, including on-chip caches, main memory, and both on…
Adaptive-Latency DRAM (AL-DRAM)
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko +4
This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was published in HPCA 2015. The key goal of AL-DRAM is to exploit the extra margin that is built into the D…
A Framework for Accelerating Bottlenecks in GPU Execution with Assist Warps
Nandita Vijaykumar, Gennady Pekhimenko, Adwait Jog +7
Modern Graphics Processing Units (GPUs) are well provisioned to support the concurrent execution of thousands of threads. Unfortunately, different bottlenecks during execution and…
Simultaneous Multi Layer Access: A High Bandwidth and Low Cost 3D-Stacked Memory Interface
Donghyuk Lee, Gennady Pekhimenko, Samira Khan +2
Limited memory bandwidth is a critical bottleneck in modern systems. 3D-stacked DRAM enables higher bandwidth by leveraging wider Through-Silicon-Via (TSV) channels, but today's sy…