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20152019
most citedImproving DRAM Performance by Parallelizing Refreshes with Accesses

150 citations · 527 across the 25 of their papers we have counts for

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Showing 2016Show all

7 papers · 1 filter

cs.AR2016★ 54 cited

Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM

Vivek Seshadri, Donghyuk Lee, Thomas Mullins +7

Bitwise operations are an important component of modern day programming. Many widely-used data structures (e.g., bitmap indices in databases) rely on fast bitwise operations on lar…

cs.AR2016★ 1 cited

Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips

Donghyuk Lee, Samira Khan, Lavanya Subramanian +5

Variation has been shown to exist across the cells within a modern DRAM chip. We empirically demonstrate a new form of variation that exists within a real DRAM chip, induced by the…

cs.AR2016★ 14 cited

Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity

Donghyuk Lee

In modern systems, DRAM-based main memory is significantly slower than the processor. Consequently, processors spend a long time waiting to access data from main memory, making the…

cs.AR2016

Adaptive-Latency DRAM (AL-DRAM)

Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko +4

This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was published in HPCA 2015. The key goal of AL-DRAM is to exploit the extra margin that is built into the D…

cs.DC2016★ 14 cited

RowHammer: Reliability Analysis and Security Implications

Yoongu Kim, Ross Daly, Jeremie Kim +6

As process technology scales down to smaller dimensions, DRAM chips become more vulnerable to disturbance, a phenomenon in which different DRAM cells interfere with each other's op…

cs.AR2016★ 1 cited

Tiered-Latency DRAM (TL-DRAM)

Donghyuk Lee, Yoongu Kim, Vivek Seshadri +3

This paper summarizes the idea of Tiered-Latency DRAM, which was published in HPCA 2013. The key goal of TL-DRAM is to provide low DRAM latency at low cost, a critical problem in m…

cs.AR2016

Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses

Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti +4

Modern DRAM cells are periodically refreshed to prevent data loss due to leakage. Commodity DDR DRAM refreshes cells at the rank level. This degrades performance significantly beca…