activity
20152021
most citedKTAN: Knowledge Transfer Adversarial Network

15 citations · 34 across the 9 of their papers we have counts for

collaborators

9 papers

cs.ET2021

A Case for 3D Integrated System Design for Neuromorphic Computing & AI Applications

Eren Kurshan, Hai Li, Mingoo Seok +1

Over the last decade, artificial intelligence has found many applications areas in the society. As AI solutions have become more sophistication and the use cases grew, they highlig…

eess.SP2020

A 6.3-Nanowatt-per-Channel 96-Channel Neural Spike Processor for a Movement-Intention-Decoding Brain-Computer-Interface Implant

Zhewei Jiang, Jiangyi Li, Pavan K. Chundi +6

This paper presents microwatt end-to-end neural signal processing hardware for deployment-stage real-time upper-limb movement intent decoding. This module features intercellular sp…

cs.NE2020★ 4 cited

Always-On, Sub-300-nW, Event-Driven Spiking Neural Network based on Spike-Driven Clock-Generation and Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device

Dewei Wang, Pavan Kumar Chundi, Sung Justin Kim +6

Always-on artificial intelligent (AI) functions such as keyword spotting (KWS) and visual wake-up tend to dominate total power consumption in ultra-low power devices. A key observa…

cs.LG2019★ 3 cited

MemNet: Memory-Efficiency Guided Neural Architecture Search with Augment-Trim learning

Peiye Liu, Bo Wu, Huadong Ma +1

Recent studies on automatic neural architectures search have demonstrated significant performance, competitive to or even better than hand-crafted neural architectures. However, mo…

cs.LG2018★ 15 cited

KTAN: Knowledge Transfer Adversarial Network

Peiye Liu, Wu Liu, Huadong Ma +2

To reduce the large computation and storage cost of a deep convolutional neural network, the knowledge distillation based methods have pioneered to transfer the generalization abil…

cs.AR2017★ 1 cited

FPGA with Improved Routability and Robustness in 130nm CMOS with Open-Source CAD Targetability

Guanshun Yu, Tom Y. Cheng, Blayne Kettlewell +3

This paper outlines an FPGA VLSI design methodology that was used to realize a fully functioning FPGA chip in 130nm CMOS with improved routability and memory robustness. The archit…