2 papers
cs.CR2025
RELIC-GNN: Efficient State Registers Identification with Graph Neural Network for Reverse Engineering
Weitao Pan, Meng Dong, Zhiliang Qiu +3
Reverse engineering of gate-level netlist is critical for Hardware Trojans detection and Design Piracy counteracting. The primary task of gate-level reverse engineering is to separ…
cs.AR2025
Critical Path Aware Timing-Driven Global Placement for Large-Scale Heterogeneous FPGAs
He Jiang, Yi Guo, Shikai Guo +4
Timing optimization during global placement is critical for achieving optimal circuit performance and remains a key challenge in modern Field Programmable Gate Array (FPGA) design.…