2 papers
cs.AR2025
A 14ns-Latency 9Gb/s 0.44mm 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
Darja Nonaca, Jérémy Guichemerre, Reinhard Wiesmayr +2
Ultra-reliable low latency communication (URLLC) is a key part of 5G wireless systems. Achieving low latency necessitates codes with short blocklengths for which polar codes with s…
cs.AR2025
StruM: Structured Mixed Precision for Efficient Deep Learning Hardware Codesign
Michael Wu, Arnab Raha, Deepak A. Mathaikutty +3
In this paper, we propose StruM, a novel structured mixed-precision-based deep learning inference method, co-designed with its associated hardware accelerator (DPU), to address the…