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Jie Zhang

3 papers hereh-index 220 citations5 works total

Matching runs newest-first, so older work may not be attached to this profile yet.

author position
  • middle author2
  • last author1

Across the 3 of 3 papers where every author was matched, so the position is known.

fields
  • cs.AR2
  • cs.ET1
same name
  • Jie Zhang — 26 papers, h 20
  • Jie Zhang — 20 papers, h 8
  • Jie Zhang — 16 papers, h 10
  • Jie Zhang — 12 papers, h 5
  • Jie Zhang — 10 papers, h 2
  • Jie Zhang — 10 papers, h 19

Either other researchers who publish under this name, or the same person where the external sources have not merged their records.

identity via Semantic Scholar / OpenAlex

activity
20242026
collaborators

3 papers

cs.ET2026

CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation

Yanjing Wang, Lizhou Wu, Wentao Hong +9

Compute eXpress Link (CXL) has emerged as a key enabler of memory disaggregation for future heterogeneous computing systems to expand memory on-demand and improve resource utilizat…

cs.AR2025

FPGA-based Emulation and Device-Side Management for CXL-based Memory Tiering Systems

Yiqi Chen, Xiping Dong, Zhe Zhou +3

The Compute Express Link (CXL) technology facilitates the extension of CPU memory through byte-addressable SerDes links and cascaded switches, creating complex heterogeneous memory…

cs.AR2024

A Novel Extensible Simulation Framework for CXL-Enabled Systems

Yuda An, Shushu Yi, Bo Mao +8

Compute Express Link (CXL) serves as a rising industry standard, delivering high-speed cache-coherent links to a variety of devices, including host CPUs, computational accelerators…

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Not affiliated with arXiv. Researcher data from Semantic Scholar (ODC-BY) and OpenAlex.