30 citations · 101 across the 20 of their papers we have counts for
8 papers · 1 filter
Efficient Table-based Function Approximation on FPGAs using Interval Splitting and BRAM Instantiation
Chetana Pradhan, Martin Letras, Jürgen Teich
This paper proposes a novel approach for the generation of memory-efficient table-based function approximation circuits for FPGAs. Given a function f(x) to be approximated in a giv…
On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains
Jorge Echavarria, Stefan Wildermann, Oliver Keszocze +3
In this paper, we present a multiplier based on a sequence of approximated accumulations. According to a given splitting point of the carry chains, the technique herein introduced…
Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning
Bernhard Schmidt, Daniel Ziener, Jürgen Teich +1
Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loo…
Massively Parallel Processor Architectures for Resource-aware Computing
Vahid Lari, Alexandru Tanase, Frank Hannig +1
We present a class of massively parallel processor architectures called invasive tightly coupled processor arrays (TCPAs). The presented processor class is a highly parameterizable…
Maintaining Virtual Areas on FPGAs using Strip Packing with Delays
Josef Angermeier, Sandor P. Fekete, Tom Kamphans +2
Every year, the computing resources available on dynamically partially reconfigurable devices increase enormously. In the near future, we expect many applications to run on a singl…
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices
Christophe Bobda, Ali Ahmadinia, Mateusz Majer +3
A new paradigm to support the communication among modules dynamically placed on a reconfigurable device at run-time is presented. Based on the network on chip (NoC) infrastructure,…