3 papers
cs.SE2026
LAUDE: LLM-Assisted Unit Test Generation and Debugging of Hardware DEsigns
Deeksha Nandal, Riccardo Revalor, Soham Dan +1
Unit tests are critical in the hardware design lifecycle to ensure that component design modules are functionally correct and conform to the specification before they are integrate…
cs.LG2025
Are LLMs Ready for Practical Adoption for Assertion Generation?
Vaishnavi Pulavarthi, Deeksha Nandal, Soham Dan +1
Assertions have been the de facto collateral for simulation-based and formal verification of hardware designs for over a decade. The quality of hardware verification, i.e., detecti…
cs.SE2025
AssertionBench: A Benchmark to Evaluate Large-Language Models for Assertion Generation
Vaishnavi Pulavarthi, Deeksha Nandal, Soham Dan +1
Assertions have been the de facto collateral for simulation-based and formal verification of hardware designs for over a decade. The quality of hardware verification, \ie, detectio…