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cs.DC2026

A CXL Memory Rack for Multi-Turn LLM Serving

Hakbeom Jang, Inho Song, Sam H. Noh +2

Long-context, multi-turn, and agentic LLM workloads increasingly reuse previously processed context, making KV-cache reuse essential for reducing redundant computation. However, th…

cs.DC2026

ITME: Inference Tiered Memory Expansion with Disaggregated CXL-Hybrid Memories

Hakbeom Jang, Younghoon Min, Sunwoong Kim +5

The rapid shift toward agentic and long-context workloads in Large Language Models (LLMs) is pushing the industry beyond the capacity of individual servers toward disaggregated sha…

cs.DC2025

TraCT: Disaggregated LLM Serving with CXL Shared Memory KV Cache at Rack-Scale

Dongha Yoon, Younghoon Min, Hoshik Kim +2

Disaggregated LLM serving improves resource efficiency by separating the compute-intensive prefill phase from the latency-critical decode phase. However, this architecture introduc…

cs.DC20254 cited

cMPI: Using CXL Memory Sharing for MPI One-Sided and Two-Sided Inter-Node Communications

Xi Wang, Bin Ma, Jongryool Kim +3

Message Passing Interface (MPI) is a foundational programming model for high-performance computing. MPI libraries traditionally employ network interconnects (e.g., Ethernet and Inf…

cs.DC2025

Accelerating Sparse Matrix-Matrix Multiplication on GPUs with Processing Near HBMs

Shiju Li, Younghoon Min, Hane Yie +5

Sparse General Matrix-Matrix Multiplication (SpGEMM) is a fundamental operation in numerous scientific computing and data analytics applications, often bottlenecked by irregular me…