2 papers
cs.DC2026
An MLIR Lowering Pipeline for Stencils at Wafer-Scale
Nicolai Stawinoga, David Katz, Anton Lydike +4
The Cerebras Wafer-Scale Engine (WSE) delivers performance at an unprecedented scale of over 900,000 compute units, all connected via a single-wafer on-chip interconnect. Initially…
cs.DC2024
Pragma driven shared memory parallelism in Zig by supporting OpenMP loop directives
David Kacs, Joseph Lee, Justs Zarins +1
The Zig programming language, which is designed to provide performance and safety as first class concerns, has become popular in recent years. Given that Zig is built upon LLVM, an…