2 papers
cs.DC2026
An MLIR Lowering Pipeline for Stencils at Wafer-Scale
Nicolai Stawinoga, David Katz, Anton Lydike +4
The Cerebras Wafer-Scale Engine (WSE) delivers performance at an unprecedented scale of over 900,000 compute units, all connected via a single-wafer on-chip interconnect. Initially…
cs.DC2025
An MLIR pipeline for offloading Fortran to FPGAs via OpenMP
Gabriel Rodriguez-Canal, David Katz, Nick Brown
With the slowing of Moore's Law, heterogeneous computing platforms such as Field Programmable Gate Arrays (FPGAs) have gained increasing interest for accelerating HPC workloads. In…