2 papers
cs.LG2026
LocalV: Exploiting Information Locality for IP-level Verilog Generation
Hanqi Lyu, Di Huang, Yaoyu Zhu +10
The generation of Register-Transfer Level (RTL) code is a crucial yet labor-intensive step in digital hardware design, traditionally requiring engineers to manually translate compl…
cs.LG2025
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs
Pengwei Jin, Di Huang, Chongxiao Li +10
The automatic generation of Verilog code using Large Language Models (LLMs) has garnered significant interest in hardware design automation. However, existing benchmarks for evalua…