activity
20142024
most citedQReg: On Regularization Effects of Quantization

3 citations · 4 across the 6 of their papers we have counts for

collaborators

6 papers

cs.CV2024

Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC

Julien Posso, Guy Bois, Yvon Savaria

This article presents a pioneering approach to real-time spacecraft pose estimation, utilizing a mixed-precision quantized neural network implemented on the FPGA components of a co…

cs.LG2024

QGen: On the Ability to Generalize in Quantization Aware Training

MohammadHossein AskariHemmat, Ahmadreza Jeddi, Reyhane Askari Hemmat +6

Quantization lowers memory usage, computational requirements, and latency by utilizing fewer bits to represent model weights and activations. In this work, we investigate the gener…

cs.AR2023

Statistical Hardware Design With Multi-model Active Learning

Alireza Ghaffari, Masoud Asgharian, Yvon Savaria

With the rising complexity of numerous novel applications that serve our modern society comes the strong need to design efficient computing platforms. Designing efficient hardware…

cs.AR2023

Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference

MohammadHossein AskariHemmat, Theo Dupuis, Yoan Fournier +8

In this paper, we present Quark, an integer RISC-V vector processor specifically tailored for sub-byte DNN inference. Quark is implemented in GlobalFoundries' 22FDX FD-SOI technolo…

cs.CV20223 cited

QReg: On Regularization Effects of Quantization

MohammadHossein AskariHemmat, Reyhane Askari Hemmat, Alex Hoffman +6

In this paper we study the effects of quantization in DNN training. We hypothesize that weight quantization is a form of regularization and the amount of regularization is correlat…

physics.space-ph20141 cited

On Delay Faults Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiations

Fatima Zahra Tazi, Claude Thibeault, Yvon Savaria +2

Experimental means to characterize delay faults induced by bit flips and SEUs in I/O blocks of SRAM-based FPGAs are proposed. A delay fault up to 6.2ns sensitized by an events chai…