3 papers
cs.LG2026
QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation
Yaoyu Zhu, Di Huang, Hanqi Lyu +16
Large language models (LLMs) trained via reinforcement learning with verifiable reward (RLVR) have achieved breakthroughs on tasks with explicit, automatable verification, such as…
cs.LG2026
LocalV: Exploiting Information Locality for IP-level Verilog Generation
Hanqi Lyu, Di Huang, Yaoyu Zhu +10
The generation of Register-Transfer Level (RTL) code is a crucial yet labor-intensive step in digital hardware design, traditionally requiring engineers to manually translate compl…
cs.AR2025
QiMeng: Fully Automated Hardware and Software Design for Processor Chip
Rui Zhang, Yuanbo Wen, Shuyao Cheng +17
Processor chip design technology serves as a key frontier driving breakthroughs in computer science and related fields. With the rapid advancement of information technology, conven…