3 citations · 12 across the 16 of their papers we have counts for
18 papers
Resistive Memory for Computing and Security: Algorithms, Architectures, and Platforms
Simranjeet Singh, Farhad Merchant, Sachin Patkar
Resistive random-access memory (RRAM) is gaining popularity due to its ability to offer computing within the memory and its non-volatile nature. The unique properties of RRAM, such…
In-Memory Mirroring: Cloning Without Reading
Simranjeet Singh, Ankit Bende, Chandan Kumar Jha +4
In-memory computing (IMC) has gained significant attention recently as it attempts to reduce the impact of memory bottlenecks. Numerous schemes for digital IMC are presented in the…
Python-based DSL for generating Verilog model of Synchronous Digital Circuits
Mandar Datar, Dhruva S. Hegde, Vendra Durga Prasad +8
We have designed a Python-based Domain Specific Language (DSL) for modeling synchronous digital circuits. In this DSL, hardware is modeled as a collection of transactions -- runnin…
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array
Ankit Bende, Simranjeet Singh, Chandan Kumar Jha +10
Memristor-aided logic (MAGIC) design style holds a high promise for realizing digital logic-in-memory functionality. The ability to implement a specific gate in a MAGIC design styl…
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende +4
Existing logic-in-memory (LiM) research is limited to generating mappings and micro-operations. In this paper, we present~\emph{MemSPICE}, a novel framework that addresses this gap…
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style
Simranjeet Singh, Chandan Kumar Jha, Ankit Bende +5
Memristor-based logic-in-memory (LiM) has become popular as a means to overcome the von Neumann bottleneck in traditional data-intensive computing. Recently, the memristor-aided lo…
IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines
Omar Ghazal, Simranjeet Singh, Tousif Rahman +8
In-memory computing for Machine Learning (ML) applications remedies the von Neumann bottlenecks by organizing computation to exploit parallelism and locality. Non-volatile memory d…
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar
Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran +4
This paper proposes an architecture that integrates neural networks (NNs) and hardware security modules using a single resistive random access memory (RRAM) crossbar. The proposed…
Finite State Automata Design using 1T1R ReRAM Crossbar
Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha +6
Data movement costs constitute a significant bottleneck in modern machine learning (ML) systems. When combined with the computational complexity of algorithms, such as neural netwo…
Hardware Security Primitives using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs
Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran +3
With rapid advancements in electronic gadgets, the security and privacy aspects of these devices are significant. For the design of secure systems, physical unclonable function (PU…
PA-PUF: A Novel Priority Arbiter PUF
Simranjeet Singh, Srinivasu Bodapati, Sachin Patkar +3
This paper proposes a 3-input arbiter-based novel physically unclonable function (PUF) design. Firstly, a 3-input priority arbiter is designed using a simple arbiter, two multiplex…
Single Storage Semi-Global Matching for Real Time Depth Processing
Prathmesh Sawant, Yashwant Temburu, Mandar Datar +3
Depth-map is the key computation in computer vision and robotics. One of the most popular approach is via computation of disparity-map of images obtained from Stereo Camera. Semi G…
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism
Niraj Sharma, Riya Jain, Madhumita Mohan +4
Many engineering and scientific applications require high precision arithmetic. IEEE~754-2008 compliant (floating-point) arithmetic is the de facto standard for performing these co…
Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies
Vinay B. Y. Kumar, Pinalkumar Engineer, Mandar Datar +4
The algorithm-to-hardware High-level synthesis (HLS) tools today are purported to produce hardware comparable in quality to handcrafted designs, particularly with user directive dr…
Expander-like Codes based on Finite Projective Geometry
Swadesh Choudhary, Hrishikesh Sharma, B. S. Adiga +1
We present a novel error correcting code and decoding algorithm which have construction similar to expander codes. The code is based on a bipartite graph derived from the subsumpti…
A Design Methodology for Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices
Hrishikesh Sharma, Sachin Patkar
Semi-parallel, or folded, VLSI architectures are used whenever hardware resources need to be saved at design time. Most recent applications that are based on Projective Geometry (P…
Finite Projective Geometry based Fast, Conflict-free Parallel Matrix Computations
Shreeniwas Sapre, Hrishikesh Sharma, Abhishek Patil +2
Matrix computations, especially iterative PDE solving (and the sparse matrix vector multiplication subproblem within) using conjugate gradient algorithm, and LU/Cholesky decomposit…
Optimal Folding of Data Flow Graphs based on Finite Projective Geometry using Lattice Embedding
Swadesh Choudhary, Hrishikesh Sharma, Sachin Patkar
A number of computations exist, especially in area of error-control coding and matrix computations, whose underlying data flow graphs are based on finite projective-geometry(PG) ba…