4 papers
Rethinking Clause Management for CDCL SAT Solvers
Yalun Cai, Xindi Zhang, Zhengyuan Shi +2
Boolean Satisfiability (SAT) solving underpins a wide range of applications in Electronic Design Automation (EDA), particularly formal verification. However, this paper observes th…
GNN-based Path-aware multi-view Circuit Learning for Technology Mapping
Wentao Jiang, Jingxin Wang, Zhang Hu +5
Traditional technology mapping suffers from systemic inaccuracies in delay estimation due to its reliance on abstract, technology-agnostic delay models that fail to capture the nua…
Functional Matching of Logic Subgraphs: Beyond Structural Isomorphism
Ziyang Zheng, Kezhi Li, Zhengyuan Shi +1
Subgraph matching in logic circuits is foundational for numerous Electronic Design Automation (EDA) applications, including datapath optimization, arithmetic verification, and hard…
Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilities
Jiaying Zhu, Ziyang Zheng, Zhengyuan Shi +2
Circuit Satisfiability (CSAT) plays a pivotal role in Electronic Design Automation. The standard workflow for solving CSAT problems converts circuits into Conjunctive Normal Form (…