3 papers
cs.LO2026
Rethinking Clause Management for CDCL SAT Solvers
Yalun Cai, Xindi Zhang, Zhengyuan Shi +2
Boolean Satisfiability (SAT) solving underpins a wide range of applications in Electronic Design Automation (EDA), particularly formal verification. However, this paper observes th…
cs.LO2025
FastLEC: Parallel Datapath Equivalence Checking with Hybrid Engines
Xindi Zhang, Furong Ye, Zhihan Chen +1
Combinational equivalence checking (CEC) remains a challenge EDA task in the formal verification of datapath circuits due to their complex arithmetic structures and the limited cap…
cs.DC2024
Datapath Combinational Equivalence Checking With Hybrid Sweeping Engines and Parallelization
Zhihan Chen, Xindi Zhang, Yuhang Qian +1
In the application of IC design for microprocessors, there are often demands for optimizing the implementation of datapath circuits, on which various arithmetic operations are perf…