activity
20032023
most citedHier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blocks

4 citations · 15 across the 10 of their papers we have counts for

collaborators

10 papers

cs.LG2023★ 1 cited

An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators

Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng +8

Parameterizable machine learning (ML) accelerators are the product of recent breakthroughs in ML. To fully enable their design space exploration (DSE), we propose a physical-design…

cs.AR2023★ 2 cited

Performance Analysis of DNN Inference/Training with Convolution and non-Convolution Operations

Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng +4

Today's performance analysis frameworks for deep learning accelerators suffer from two significant limitations. First, although modern convolutional neural network (CNNs) consist o…

cs.LG2023★ 2 cited

K-SpecPart: Supervised embedding algorithms and cut overlay for improved hypergraph partitioning

Ismail Bustany, Andrew B. Kahng, Ioannis Koutis +2

State-of-the-art hypergraph partitioners follow the multilevel paradigm that constructs multiple levels of progressively coarser hypergraphs that are used to drive cut refinement o…

cs.AR2023★ 1 cited

A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route

Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng +1

Due to the unavailability of routing information in design stages prior to detailed routing (DR), the tasks of timing prediction and optimization pose major challenges. Inaccurate…

cs.AR2023★ 3 cited

PROBE3.0: A Systematic Framework for Design-Technology Pathfinding with Improved Design Enablement

Suhyeong Choi, Jinwook Jung, Andrew B. Kahng +4

We propose a systematic framework to conduct design-technology pathfinding for PPAC in advanced nodes. Our goal is to provide configurable, scalable generation of process design ki…

eess.SY2023★ 4 cited

Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blocks

Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang

In a typical RTL to GDSII flow, floorplanning or macro placement is a critical step in achieving decent quality of results (QoR). Moreover, in today's physical synthesis flows (e.g…