3 papers
cs.AR2026
FormalRTL: Verified RTL Synthesis at Scale
Kezhi Li, Min Li, Xiangyu Wen +4
Large language models (LLMs) have demonstrated significant potential in automating hardware synthesis, yet substantial barriers remain for industrial-scale, datapath-centric design…
cs.AI2025
Reasoning Scaffolding: Distilling the Flow of Thought from LLMs
Xiangyu Wen, Junhua Huang, Zeju Li +6
The prevailing approach to distilling reasoning from Large Language Models (LLMs)-behavioral cloning from textual rationales-is fundamentally limited. It teaches Small Language Mod…
cs.SE2024
VerilogReader: LLM-Aided Hardware Test Generation
Ruiyang Ma, Yuxin Yang, Ziqian Liu +4
Test generation has been a critical and labor-intensive process in hardware design verification. Recently, the emergence of Large Language Model (LLM) with their advanced understan…