3 papers
physics.ins-det2018
A Phase Lookahead DTC for Fast Settling Switched Loop DPLL
Pallavi Paliwal, Vivek Yadav, Shalabh Gupta
In most digital-to-time converter (DTC) based applications, apart from maintaining low integral non-linearity (INL), it is also required of the system to achieve a wide frequency t…
eess.SY2018
Stability Analysis for Fast Settling Switched DPLL
Pallavi Paliwal, Debasattam Pal, Shalabh Gupta
In current generation digital phase locked loop (DPLL) architectures, techniques like adaptive loop bandwidth with loop order switching and switched phase-detection are employed to…
physics.ins-det2012
Trade-off between Settling Time and Jitter in Phase Locked Loop
Pallavi Paliwal, Mohanrao Sattineni, Shalabh Gupta
Most PLL architectures have inherent trade-off between settling time and jitter. This trade-off is ignored by commonly used Figure of Merit (FoM) for PLL, which considers only jitt…