3 papers
cs.SE2014
Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL
Abhishek Jain, Dr. Hima Gupta, Sandeep Jana +1
With semiconductor industry trend of smaller the better, from an idea to a final product, more innovation on product portfolio and yet remaining competitive and profitable are few…
cs.OH2014
Accelerating SystemVerilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator
Abhishek Jain, Piyush Kumar Gupta, Dr. Hima Gupta +1
In this paper we present the development of Acceleratable UVCs from standard UVCs in SystemVerilog and their usage in UVM based Verification Environment of Image Signal Processing…
cs.OH2013
Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs
Abhishek Jain, Giuseppe Bonanno, Hima Gupta +1
In this paper,we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient verification of Image Signal Processing IP'…