2 papers
cs.LG2026
QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression for Circuit Design
Lei Huang, Rui Zhang, Jiaming Guo +9
Large language models (LLMs) have shown promising capabilities in hardware description language (HDL) generation. However, existing approaches often rely on free-form natural langu…
cs.LG2025
QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation
Yang Zhang, Rui Zhang, Jiaming Guo +10
The remarkable progress of Large Language Models (LLMs) presents promising opportunities for Verilog code generation which is significantly important for automated circuit design.…