activity
20132022
most citedFPGA Implementation of the CAR Model of the Cochlea

34 citations · 77 across the 13 of their papers we have counts for

collaborators
Showing cs.NEShow all

14 papers · 1 filter

cs.NE2022★ 4 cited

Making a Spiking Net Work: Robust brain-like unsupervised machine learning

Peter G. Stratton, Andrew Wabnitz, Chip Essam +2

The surge in interest in Artificial Intelligence (AI) over the past decade has been driven almost exclusively by advances in Artificial Neural Networks (ANNs). While ANNs set state…

cs.NE2016★ 11 cited

A Stochastic Approach to STDP

Runchun Wang, Chetan Singh Thakur, Tara Julia Hamilton +2

We present a digital implementation of the Spike Timing Dependent Plasticity (STDP) learning rule. The proposed digital implementation consists of an exponential decay generator ar…

cs.NE2016★ 1 cited

Investigation of event-based memory surfaces for high-speed tracking, unsupervised feature extraction and object recognition

Saeed Afshar, Gregory Cohen, Tara Julia Hamilton +2

In this paper we compare event-based decaying and time based-decaying memory surfaces for high-speed eventbased tracking, feature extraction, and object classification using an eve…

cs.NE2015★ 1 cited

A Reconfigurable Mixed-signal Implementation of a Neuromorphic ADC

Ying Xu, Chetan Singh Thakur, Tara Julia Hamilton +3

We present a neuromorphic Analogue-to-Digital Converter (ADC), which uses integrate-and-fire (I&F) neurons as the encoders of the analogue signal, with modulated inhibitions to dec…

cs.NE2015★ 1 cited

A compact aVLSI conductance-based silicon neuron

Runchun Wang, Chetan Singh Thakur, Tara Julia Hamilton +2

We present an analogue Very Large Scale Integration (aVLSI) implementation that uses first-order lowpass filters to implement a conductance-based silicon neuron for high-speed neur…

cs.NE2015★ 12 cited

A neuromorphic hardware architecture using the Neural Engineering Framework for pattern recognition

Runchun Wang, Chetan Singh Thakur, Tara Julia Hamilton +2

We present a hardware architecture that uses the Neural Engineering Framework (NEF) to implement large-scale neural networks on Field Programmable Gate Arrays (FPGAs) for performin…