activity
20132019
most citedA neuromorphic hardware architecture using the Neural Engineering Framework for pattern recognition

12 citations · 41 across the 11 of their papers we have counts for

collaborators

12 papers

cs.LG2019

Single-bit-per-weight deep convolutional neural networks without batch-normalization layers for embedded systems

Mark D. McDonnell, Hesham Mostafa, Runchun Wang +1

Batch-normalization (BN) layers are thought to be an integrally important layer type in today's state-of-the-art deep convolutional neural networks for computer vision tasks such a…

cs.NE2018★ 1 cited

Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain

Chetan Singh Thakur, Jamal Molin, Gert Cauwenberghs +12

Neuromorphic engineering (NE) encompasses a diverse range of approaches to information processing that are inspired by neurobiological systems, and this feature distinguishes neuro…

cs.NE2018★ 2 cited

An FPGA-based Massively Parallel Neuromorphic Cortex Simulator

Runchun Wang, Chetan Singh Thakur, Andre van Schaik

This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as comple…

cs.NE2016★ 11 cited

A Stochastic Approach to STDP

Runchun Wang, Chetan Singh Thakur, Tara Julia Hamilton +2

We present a digital implementation of the Spike Timing Dependent Plasticity (STDP) learning rule. The proposed digital implementation consists of an exponential decay generator ar…

cs.NE2015★ 1 cited

A Reconfigurable Mixed-signal Implementation of a Neuromorphic ADC

Ying Xu, Chetan Singh Thakur, Tara Julia Hamilton +3

We present a neuromorphic Analogue-to-Digital Converter (ADC), which uses integrate-and-fire (I&F) neurons as the encoders of the analogue signal, with modulated inhibitions to dec…

cs.NE2015★ 1 cited

A compact aVLSI conductance-based silicon neuron

Runchun Wang, Chetan Singh Thakur, Tara Julia Hamilton +2

We present an analogue Very Large Scale Integration (aVLSI) implementation that uses first-order lowpass filters to implement a conductance-based silicon neuron for high-speed neur…