2 papers
cs.LG2026
Continuous-Flow Data-Rate-Aware CNN Inference on FPGA
Tobias Habermann, Michael Mecik, Zhenyu Wang +3
Among hardware accelerators for deep-learning inference, data flow implementations offer low latency and high throughput capabilities. In these architectures, each neuron is mapped…
cs.AR2025
Implementation and Analysis of Thermometer Encoding in DWN FPGA Accelerators
Michael Mecik, Martin Kumm
Fully parallel neural network accelerators on field-programmable gate arrays (FPGAs) offer high throughput for latency-critical applications but face hardware resource constraints.…