2 papers
cs.LG2026
Continuous-Flow Data-Rate-Aware CNN Inference on FPGA
Tobias Habermann, Michael Mecik, Zhenyu Wang +3
Among hardware accelerators for deep-learning inference, data flow implementations offer low latency and high throughput capabilities. In these architectures, each neuron is mapped…
cs.AR2026
Data-Rate-Aware High-Speed CNN Inference on FPGAs
Tobias Habermann, Martin Kumm
Dataflow-based CNN accelerators on FPGAs achieve low latency and high throughput by mapping computations of each layer directly to corresponding hardware units. However, layers suc…