3 papers
cs.AR2026
Pooling Engram Conditional Memory in Large Language Models using CXL
Ruiyang Ma, Teng Ma, Zhiyuan Su +11
Engram conditional memory has emerged as a promising component for LLMs by decoupling static knowledge lookup from dynamic computation. Since Engram exhibits sparse access patterns…
cs.AR2025
Wit-HW: Bug Localization in Hardware Design Code via Witness Test Case Generation
Ruiyang Ma, Daikang Kuang, Ziqian Liu +3
Debugging hardware designs requires significant manual effort during hardware development. After engineers identify a bug-triggering test case in simulation-based hardware verifica…
cs.SE2024
VerilogReader: LLM-Aided Hardware Test Generation
Ruiyang Ma, Yuxin Yang, Ziqian Liu +4
Test generation has been a critical and labor-intensive process in hardware design verification. Recently, the emergence of Large Language Model (LLM) with their advanced understan…