2 papers
cs.AR2026
Link Quality Aware Pathfinding for Chiplet Interconnects
Aaron Yen, Jooyeon Jeong, Puneet Gupta
As chiplet-based integration advances, designers must select among short-reach die-to-die interconnect technologies with widely varying shoreline and areal bandwidth density, energ…
cs.AR2025
YAP+: Pad-Layout-Aware Yield Modeling and Simulation for Hybrid Bonding
Zhichao Chen, Puneet Gupta
Three-dimensional (3D) integration continues to advance Moore's Law by facilitating dense interconnects and enabling multi-tier system architectures. Among the various integration…