2 papers
cs.AR2026
Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs
Xiaoke Wang, Raveena Raikar, Markus Rein +3
Multi-die FPGAs enable device scaling beyond reticle limits but introduce severe interconnect overhead across die boundaries. Inter-die connections, commonly referred to as super-l…
cs.AR2025
QUADOL: A Quality-Driven Approximate Logic Synthesis Method Exploiting Dual-Output LUTs for Modern FPGAs
Jian Shi, Xuan Wang, Chang Meng +1
Approximate computing is a new computing paradigm. One important area of it is designing approximate circuits for FPGA. Modern FPGAs support dual-output LUT, which can significantl…