3 papers
cs.AR2026
Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs
Xiaoke Wang, Raveena Raikar, Markus Rein +3
Multi-die FPGAs enable device scaling beyond reticle limits but introduce severe interconnect overhead across die boundaries. Inter-die connections, commonly referred to as super-l…
cs.ET2025
Length-Matching Routing for Programmable Photonic Circuits Using Best-First Strategy
Xiaoke Wang, Dirk Stroobandt
In the realm of programmable photonic integrated circuits (PICs), precise wire length control is crucial for the performance of on-chip programmable components such as optical ring…
eess.SY2025
Dense or Sparse? Post-Packing Interconnection Analysis in FPGAs
X. Wang, D. Stroobandt
Packing is a crucial step of FPGA design, directly impacting interconnect complexity, routing congestion, and overall performance. This paper presents a post-packing interconnect-a…