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cs.AR2025
Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
Kshitij Raj, Atri Chatterjee, Patanjali SLPSK +2
Designing secure architectures for system-on-chip (SoC) platforms is a highly intricate and time-intensive task, often requiring months of development and meticulous verification.…
cs.AR2025
Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation
Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta +2
Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D hetero…