3 papers
cs.PL2026
Vectorization of Verilog Designs and its Effects on Verification and Synthesis
Maria Fernanda Oliveira Guimarães, Ulisses Rosa, Ian Trudel +4
Vectorization is a compiler optimization that replaces multiple operations on scalar values with a single operation on vector values. Although common in traditional compilers such…
cs.AR2025
Bottom-Up Generation of Verilog Designs for Testing EDA Tools
João Victor Amorim Vieira, Luiza de Melo Gomes, Rafael Sumitani +4
Testing Electronic Design Automation (EDA) tools rely on benchmarks -- designs written in Hardware Description Languages (HDLs) such as Verilog, SystemVerilog, or VHDL. Although co…
cs.AR2024
ChiBench: a Benchmark Suite for Testing Electronic Design Automation Tools
Rafael Sumitani, João Victor Amorim, Augusto Mafra +2
Electronic Design Automation (EDA) tools are software applications used by engineers in the design, development, simulation, and verification of electronic systems and integrated c…