4 papers
SAAP: An Efficient Spatial-Aware Analytic Partitioning Algorithm of VLSI Netlists for Parallel Routing
Chen Liu, Hongxin Kong, Lang Feng +2
As VLSI designs grow in complexity, partitioning is widely adopted to accelerate physical design through parallel computing. However, traditional hypergraph partitioning methods of…
Towards Secure and Efficient DNN Accelerators via Hardware-Software Co-Design
Wei Xuan, Zihao Xuan, Rongliang Fu +8
The rapid deployment of deep neural network (DNN) accelerators in safety-critical domains such as autonomous vehicles, healthcare systems, and financial infrastructure necessitates…
A High Efficient and Scalable Obstacle-Avoiding VLSI Global Routing Flow
Junhao Guo, Hongxin Kong, Lang Feng
Routing is a crucial step in the VLSI design flow. With the advancement of manufacturing technologies, more constraints have emerged in design rules, particularly regarding obstacl…
SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
Wei Xuan, Zhongrui Wang, Lang Feng +6
Ensuring the confidentiality and integrity of DNN accelerators is paramount across various scenarios spanning autonomous driving, healthcare, and finance. However, current security…